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Circuits

Compile a CRE8VM program to Verilog and a netlist scene, then read each design's artifact hashes, simulated cycles and recorded hardware runs.

Who it is for

Hardware designers and silicon reviewers

Getting started

All apps

Declared views

Runtime chip

The booted runtime drawn as a gate schematic from declared app metadata.
circuit.chipRole customFormat document/view/chip

Circuit — Transparent Silicon

circuit.indexRole role not declaredFormat document/view/circuit

Designs

Synthesize a program into a circuit and open any stored design.
circuit.indexRole listFormat document/view/circuit/list

Design

circuit.itemRole detailFormat documentRequires a real route parameter; open through its app./view/circuit/{design_id}

Declared Connections

Connections are declared by the owning app. Their presence does not grant permission to execute them.

Circuit.AsicHandoff

Circuit.EmitScene

Circuit.Get

Circuit.List

Circuit.RunPisCore

Circuit.Simulate

Circuit.Status

Circuit.Synthesize

Circuit.SynthesizePisCore

Circuit.VerifyPisOccurrence

Circuit.ViewPatch

Data model ownership

These storage and model facts come from app declarations. They do not establish current storage contents or operational readiness.

Declared storage

Authority hyperPreferred truth hyperApp owner Circuit

Hyper vertex kinds read

CircuitDesign

Hyper vertex kinds written

ByteAtom, CircuitDesign, CircuitPisCoreRun, EvidenceClaim, ExecutionEvidencePromotion, ExecutionObservation, ExecutionOccurrence, ExecutionWorkKey, IrHash

Hyper edge kinds written

None declared.

Asset namespaces read

None declared.

Asset namespaces minted

None declared.

SQL projection

Declared role noneDDL declarations 0

Model warnings

No model warnings were reported.

Structure review

No structure diagnostics were reported for this app.

Reference provenance

Generated from cre8.app_structure.v1 for app Circuit. Declaration reference only; not execution, browser, or release evidence.