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crates/cre8-app-circuit/src/designs.rs
Items
const KIND_CIRCUIT_DESIGN const SCENE_SCHEMA const MAX_SOURCE_BYTES const MAX_VM_STEPS struct CircuitDesign impl CircuitDesign struct SynthesisOutcome struct BitstreamTarget impl BitstreamTarget struct DieOutcome const ADD_SRC
Functions
By call-graph weight (PageRank; 1.0 is the average function). 31 functions in all.
| function | kind | lines | cyclomatic | callers | callees | weight | crystal |
|---|---|---|---|---|---|---|---|
| compile_opssrc/designs.rs:219 | fn | 9 | 1 | 8 | 0 | 4.6 | |
| load_designsrc/designs.rs:720 | fn | 5 | 1 | 13 | 4 | 2.6 | |
| design_from_verilog_with_targetsrc/designs.rs:374 | fn | 95 | 6 | 2 | 5 | 2 | |
| CircuitDesign::atlas_lineagesrc/designs.rs:96 | method | 16 | 1 | 3 | 1 | 1.8 | |
| synthesize_with_targetsrc/designs.rs:296 | fn | 33 | 3 | 1 | 2 | 1.7 | |
| CircuitDesign::atlas_framesrc/designs.rs:114 | method | 3 | 1 | 2 | 2 | 1.6 | |
| CircuitDesign::from_propssrc/designs.rs:173 | method | 29 | 1 | 3 | 0 | 1.5 | |
| synthesizesrc/designs.rs:282 | fn | 10 | 1 | 4 | 1 | 1.4 | |
| list_designssrc/designs.rs:726 | fn | 13 | 1 | 4 | 4 | 1.4 | |
| CircuitDesign::summarysrc/designs.rs:119 | method | 31 | 1 | 3 | 2 | 1.3 | |
| design_vidsrc/designs.rs:678 | fn | 3 | 1 | 2 | 1 | 1.3 | |
| save_designsrc/designs.rs:682 | fn | 5 | 1 | 3 | 4 | 1.3 | |
| BitstreamTarget::from_inputsrc/designs.rs:256 | method | 11 | 1 | 3 | 0 | 1.3 | |
| CircuitDesign::detailsrc/designs.rs:152 | method | 12 | 3 | 1 | 2 | 1.2 | |
| design_from_verilogsrc/designs.rs:342 | fn | 27 | 1 | 1 | 1 | 0.9 | |
| CircuitDesign::to_propssrc/designs.rs:165 | method | 7 | 2 | 2 | 1 | 0.9 | |
| BitstreamTarget::pis_core_defaultsrc/designs.rs:248 | method | 3 | 1 | 2 | 0 | 0.8 | |
| build_bitstreamsrc/designs.rs:554 | fn | 105 | 7 | 1 | 2 | 0.8 | |
| record_asicsrc/designs.rs:712 | fn | 7 | 1 | 1 | 2 | 0.7 | |
| record_simulationsrc/designs.rs:693 | fn | 12 | 1 | 1 | 3 | 0.6 | |
| BitstreamTarget::labelsrc/designs.rs:269 | method | 8 | 4 | 0 | 0 | 0.5 | |
| synthesizesrc/designs.rs:476 | fn | 12 | 1 | 0 | 0 | 0.5 | |
| synthesize_with_targetsrc/designs.rs:491 | fn | 11 | 1 | 0 | 1 | 0.5 | |
| design_from_verilogsrc/designs.rs:507 | fn | 15 | 1 | 0 | 0 | 0.5 | |
| design_from_verilog_with_targetsrc/designs.rs:525 | fn | 14 | 1 | 0 | 1 | 0.5 | |
| build_bitstreamsrc/designs.rs:661 | fn | 14 | 2 | 0 | 0 | 0.5 | |
| bitstream_target_reads_input_over_fallback_and_strips_dashessrc/designs.rs:743 | fn | 11 | 1 | 0 | 2 | 0.5 | |
| synthesize_builds_scene_and_atoms_without_truthsrc/designs.rs:762 | fn | 28 | 1 | 0 | 4 | 0.5 | |
| synthesize_is_deterministic_per_sourcesrc/designs.rs:792 | fn | 8 | 1 | 0 | 2 | 0.5 | |
| synthesize_rejects_empty_and_oversized_sourcesrc/designs.rs:802 | fn | 6 | 1 | 0 | 2 | 0.5 | |
| design_props_round_tripsrc/designs.rs:810 | fn | 63 | 1 | 0 | 4 | 0.5 |
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