rust 1,847,280 · typescript 232,434 · javascript 131,101 · python 19,227 · 6,362 files · digest 755e2ee30522 · built in 2.3 s · crystals off
cre8-app-circuit circuit cargo crate
CircuitApp — circuit.scene.v1: synthesize any IR program to Verilog + a render-ready netlist scene in-process, store the artifacts as content-addressed atoms, and book a durable CircuitDesign vertex. Transparent Circuit R2, 2026-07-16.
Neighbourhood
Left: crates that declare this one. Right: crates it declares (dev-dependencies included). Edge width grows with resolved calls.
Declared but never named in this crate's source: cre8-app-virtual_bridge (normal).
Files
File call graph
Resolved calls between this crate's files, callers left of callees.
Heaviest functions
By call-graph weight (PageRank; 1.0 is the average function). 311 functions in all.
| function | kind | lines | cyclomatic | callers | callees | weight | crystal |
|---|---|---|---|---|---|---|---|
| expr_textsrc/fsm_svg.rs:48 | fn | 25 | 21 | 3 | 1 | 6.8 | |
| binsrc/fsm_svg.rs:44 | fn | 3 | 1 | 1 | 1 | 6.3 | |
| compile_opssrc/designs.rs:219 | fn | 9 | 1 | 8 | 0 | 4.6 | |
| schematic_svgsrc/scene_svg.rs:491 | fn | 69 | 9 | 9 | 5 | 3.3 | |
| load_designsrc/designs.rs:720 | fn | 5 | 1 | 13 | 4 | 2.6 | |
| connectsrc/connection.rs:92 | fn | 9 | 3 | 9 | 1 | 2.6 | |
| depthsrc/runtime_chip.rs:103 | nested fn | 25 | 3 | 1 | 0 | 2.5 | |
| build_handoff_reportsrc/asic.rs:190 | fn | 162 | 28 | 5 | 4 | 2.4 | |
| boot_rankssrc/runtime_chip.rs:101 | fn | 33 | 2 | 3 | 1 | 2.3 | |
| op_tablesrc/pis_core.rs:180 | fn | 31 | 1 | 5 | 0 | 2.3 | |
| encode_opssrc/pis_core.rs:126 | fn | 6 | 1 | 1 | 0 | 2.2 | |
| live_region_html_with_runsrc/view_templates.rs:578 | fn | 18 | 3 | 4 | 7 | 2.1 | |
| atom_link_htmlsrc/view_templates.rs:832 | fn | 10 | 2 | 3 | 0 | 2.1 | |
| build_coresrc/pis_core.rs:92 | fn | 32 | 2 | 7 | 1 | 2 | |
| design_from_verilog_with_targetsrc/designs.rs:374 | fn | 95 | 6 | 2 | 5 | 2 | |
| scene_section_htmlsrc/scene_svg.rs:567 | fn | 29 | 5 | 2 | 3 | 2 | |
| emit_scene_atom_to_worldsrc/bridge.rs:125 | fn | 109 | 9 | 2 | 3 | 2 | |
| sim_at_cyclesrc/sim.rs:169 | fn | 34 | 7 | 5 | 2 | 1.9 | |
| CircuitDesign::atlas_lineagesrc/designs.rs:96 | method | 16 | 1 | 3 | 1 | 1.8 | |
| build_default_sdcsrc/asic.rs:86 | fn | 32 | 11 | 3 | 0 | 1.8 | |
| fxsrc/scene_svg.rs:152 | fn | 4 | 2 | 3 | 0 | 1.8 | |
| active_state_from_waveform_cyclesrc/fsm_svg.rs:361 | fn | 3 | 1 | 2 | 0 | 1.7 | |
| build_detail_treesrc/view_templates.rs:256 | fn | 53 | 4 | 7 | 13 | 1.7 | |
| synthesize_with_targetsrc/designs.rs:296 | fn | 33 | 3 | 1 | 2 | 1.7 | |
| dispatch_bridge_eventssrc/bridge.rs:340 | fn | 26 | 2 | 2 | 3 | 1.7 | |
| scrubber_for_rangesrc/view_templates.rs:770 | fn | 22 | 4 | 2 | 0 | 1.7 | |
| CircuitDesign::atlas_framesrc/designs.rs:114 | method | 3 | 1 | 2 | 2 | 1.6 | |
| emit_activity_to_world_innersrc/bridge.rs:272 | fn | 62 | 6 | 2 | 2 | 1.5 | |
| CircuitDesign::from_propssrc/designs.rs:173 | method | 29 | 1 | 3 | 0 | 1.5 | |
| synthesizesrc/designs.rs:282 | fn | 10 | 1 | 4 | 1 | 1.4 | |
| fsm_section_htmlsrc/fsm_svg.rs:316 | fn | 42 | 5 | 5 | 4 | 1.4 | |
| parse_inputssrc/sim.rs:46 | fn | 26 | 9 | 5 | 0 | 1.4 | |
| build_default_yosys_scriptsrc/asic.rs:122 | fn | 14 | 1 | 2 | 0 | 1.4 | |
| runtime_scenesrc/runtime_chip.rs:136 | fn | 72 | 5 | 4 | 1 | 1.4 | |
| SignedPisCoreRunRequestV1::verifysrc/pis_run.rs:207 | method | 14 | 1 | 5 | 3 | 1.4 | |
| list_designssrc/designs.rs:726 | fn | 13 | 1 | 4 | 4 | 1.4 | |
| usize_fieldsrc/pis_core.rs:153 | fn | 7 | 3 | 1 | 0 | 1.4 | |
| circuit_detail_patch_framesrc/view_templates.rs:809 | fn | 20 | 5 | 1 | 4 | 1.4 | |
| CircuitDesign::summarysrc/designs.rs:119 | method | 31 | 1 | 3 | 2 | 1.3 | |
| design_vidsrc/designs.rs:678 | fn | 3 | 1 | 2 | 1 | 1.3 |
Outside the workspace
anyhow base64 cre8-vm hyperdb serde serde_json tiny_http